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STK16C88-3 256 kbit (32k x 8) autostore+ nvsram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-50594 rev. ** revised january 29, 2009 features fast 35ns read access and r/w cycle time directly replaces battery-ba cked sram modules such as dallas/maxim ds1230w automatic nonvolatile store on power loss nonvolatile store under software control automatic recall to sram on power up unlimited read/write endurance 1,000,000 store cycles 100 year data retention single 3.3v+ 0.3v power supply commercial and industrial temperatures 28-pin (600 mil) pdip package rohs compliance functional description the cypress STK16C88-3 is a 256kb fast static ram with a nonvolatile element in each memory cell. the embedded nonvolatile elements incorporate quantumtrap ? technology producing the world?s most reliable nonvolatile memory. the sram provides unlimited read and write cycles, while independent, nonvolatile data re sides in the highly reliable quantumtrap cell. data transfers from the sram to the nonvolatile elements (the store operation) takes place automatically at power down. on power up, data is restored to the sram (the recall operat ion) from the nonvolatile memory. both the store and recall operations are also available under software control. logic block diagram [+] feedback
STK16C88-3 document number: 001-50594 rev. ** page 2 of 14 pin configurations figure 1. pin diagram - 28-pin pdip table 1. pin definitions - 28-pin pdip pin name alt io type description a 0 ?a 14 input address inputs. used to select one of the 32,768 bytes of the nvsram. dq 0 -dq 7 input or output bidirectional data io lines . used as input or output lines depending on operation. we w input write enable input, active low . when the chip is enabled and we is low, data on the io pins is written to the specific address location. ce e input chip enable input, active low . when low, selects the chip. when high, deselects the chip. oe g input output enable, active low . the active low oe input enables the data output buffers during read cycles. deasserting oe high causes the io pins to tri-state. v ss ground ground for the device . the device is connected to ground of the system. v cc power supply power supply inputs to the device . $ $ $ $ '4 '4 '4 $ $ $ $ $ $ $ $ '4 '4 9 66 $ &( $ $ 9 && :( '4 '4 '4 2( 723 [+] feedback
STK16C88-3 document number: 001-50594 rev. ** page 3 of 14 device operation the autostore+ STK16C88-3 is a fast 32k x 8 sram that does not lose its data on power down. the data is preserved in integral quantumtrap non-volatile storage elements when power is lost. automatic store on power down and automatic recall on power up guarantee data integrit y without the use of batteries. sram read the STK16C88-3 performs a read cycle whenever ce and oe are low while we is high. the address specified on pins a 0?14 determines the 32,768 data bytes accessed. when the read is initiated by an address transition, the outputs are valid after a delay of t aa (read cycle 1). if the read is initiated by ce or oe , the outputs are valid at t ace or at t doe , whichever is later (read cycle 2). the data outputs repeatedly respond to address changes within the t aa access time without the need for transi- tions on any control input pins, and remains valid until another address change or until ce or oe is brought high. sram write a write cycle is performed whenever ce and we are low. the address inputs must be stable prior to entering the write cycle and must remain stable until either ce or we goes high at the end of the cycle. the data on the common io pins dq 0?7 are written into the memory if it has valid t sd , before the end of a we controlled write or before the end of an ce controlled write. keep oe high during the entire write cycle to avoid data bus contention on common io lines. if oe is left low, internal circuitry turns off the output buffers t hzwe after we goes low. autostore+ operation the STK16C88-3?s automatic store on power down is com- pletely transparent to the system. the store initiation takes less than 500 ns when power is lost (v cc STK16C88-3 is in a write state at the end of power up recall, the sram data is corrupted. to help avoid this situation, a 10 kohm resistor is connected either between we and system v cc or between ce and system v cc . software store data is transferred from the sram to the nonvolatile memory by a software address sequence. the STK16C88-3 software store cycle is initiated by executing sequential ce controlled read cycles from six specific address locations in exact order. during the store cycle, an erase of the previous nonvolatile data is first performed followed by a program of the nonvolatile elements. when a store cycle is initiated, input and output are disabled until the cycle is completed. because a sequence of reads from specific addresses is used for store initiation, it is import ant that no other read or write accesses intervene in the sequence. if they intervene, the sequence is aborted and no store or recall takes place. to initiate the software stor e cycle, the following read sequence is performed: 1. read address 0x0e38, valid read 2. read address 0x31c7, valid read 3. read address 0x03e0, valid read 4. read address 0x3c1f, valid read 5. read address 0x303f, valid read 6. read address 0x0fc0, initiate store cycle the software sequence is clocked with ce controlled reads. when the sixth address in the sequence is entered, the store cycle commences and the chip is disabled. it is important that read cycles and not write cycl es are used in the sequence. it is not necessary that oe is low for a valid sequence. after the t store cycle time is fulfilled, the sram is again activated for read and write operation. software recall data is transferred from the nonvolatile memory to the sram by a software address sequence. a software recall cycle is initiated with a sequence of read operations in a manner similar to the software store initiation. to initiate the recall cycle, the following sequence of ce controlled read operations is performed: 1. read address 0x0e38, valid read 2. read address 0x31c7, valid read 3. read address 0x03e0, valid read 4. read address 0x3c1f, valid read 5. read address 0x303f, valid read 6. read address 0x0c63, initiate recall cycle internally, recall is a two step procedure. first, the sram data is cleared, and then the nonvolatile information is transferred into the sram cells. after the t recall cycle time, the sram is once again ready for read and write operations. the recall operation does not alter the data in the nonvolatile elements. the nonvolatile data can be recalled an unlimited number of times. [+] feedback
STK16C88-3 document number: 001-50594 rev. ** page 4 of 14 hardware protect the STK16C88-3 offers hardware protection against inadvertent store operation and sram writes during low voltage conditions. when v cap STK16C88-3 is a high speed memory. it must have a high frequency bypass capacitor of approximately 0.1 f connected between v cc and v ss, using leads and traces that are as short as possible. as with all high speed cmos ics, careful routing of power, ground, and signals helps prevent noise problems. low average active power cmos technology provides the STK16C88-3 the benefit of drawing significantly less curren t when it is cycled at times longer than 50 ns. figure 2 and figure 3 shows the relationship between i cc and read or write cycle time. worst case current consumption is shown for both cmos and ttl input levels (commercial temperature range, vcc = 5.5v, 100% duty cycle on chip enable). only standby current is drawn when the chip is disabled. the overall average current drawn by the STK16C88-3 depends on the following items: 1. the duty cycle of chip enable 2. the overall cycle rate for accesses 3. the ratio of reads to writes 4. cmos versus ttl input levels 5. the operating temperature 6. the v cc level 7. io loading figure 3. current versus cycle time (write) best practices nvsram products have been used effectively for over 15 years. while ease-of-use is one of the product?s main system values, experience gained working with hundreds of applica- tions has resulted in the following suggestions as best practices: the nonvolatile cells in an nvsram are programmed on the test floor during final test and quality assurance. incoming inspection routines at customer or contract manufacturer?s sites will sometimes reprogram these values. final nv patterns are typically repeating patterns of aa, 55, 00, ff, a5, or 5a. end product?s firmware should not assume a nv array is in a set programmed state. routines that check memory content values to determ ine first time system config- uration and cold or warm boot status, should always program a unique nv pattern (for example, complex 4-byte pattern of 46 e6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently. power up boot firmware routines should rewrite the nvsram into the desired state. while the nvsram is shipped in a preset state, best practice is to again rewrite the nvsram into the desired state as a sa feguard against events that might flip the bit inadvertently (program bugs or incoming inspection routines). figure 2. current versus cycle time (read) [+] feedback
STK16C88-3 document number: 001-50594 rev. ** page 5 of 14 table 2. software stor e/recall mode selection ce we a 13 ? a 0 mode io notes l h 0x0e38 0x31c7 0x03e0 0x3c1f 0x303f 0x0fc0 read sram read sram read sram read sram read sram nonvolatile store output data output data output data output data output data output data [1, 2] l h 0x0e38 0x31c7 0x03e0 0x3c1f 0x303f 0x0c63 read sram read sram read sram read sram read sram nonvolatile recall output data output data output data output data output data output data [1, 2] notes 1. the six consecutive addresses must be in the order listed. we must be high during all six consecutive ce controlled cycles to enable a nonvolatile cycle. 2. while there are 15 addresses on the STK16C88-3, only the lower 14 are used to control software modes. [+] feedback
STK16C88-3 document number: 001-50594 rev. ** page 6 of 14 maximum ratings exceeding maximum ratings may shorten the useful life of the device. these user guidelines are not tested. storage temperature ................................. ?65 c to +150 c temperature under bias .............................. ?55 c to +125 c supply voltage on v cc relative to gnd.......... ?0.5v to 4.5v voltage on input relative to vss ............?0.6v to v cc + 0.5v voltage on dq 0-7 ...................................?0.5v to vcc + 0.5v power dissipation ......................................................... 1.0w dc output current (1 output at a time, 1s duration) .... 15 ma operating range range ambient temperature v cc commercial 0 c to +70 c 3.0v to 3.6v industrial -40 c to +85 c 3.0v to 3.6v dc electrical characteristics over the operating range (v cc = 3.0v to 3.6v) parameter description test conditions min max unit i cc1 average v cc current t rc = 35 ns dependent on output loading and cycle rate. values obtained without output loads. i out = 0 ma. commercial 50 ma industrial 52 ma i cc2 average v cc current during store all inputs do not care, v cc = max average current for duration t store 3ma i cc3 average v cc current at t rc = 200 ns, 5v, 25c typical we > (v cc ? 0.2v). all other inputs cycling. dependent on output loading and cycle rate. values obtained without output loads. 8ma i sb1 [3] average v cc current (standby, cycling ttl input levels) t rc =35ns, ce > v ih commercial 18 ma industrial 19 ma i sb2 [3] v cc standby current (standby, stable cmos input levels) ce > (v cc ? 0.2v). all others v in < 0.2v or > (v cc ? 0.2v). 1 ma i ix input leakage current v cc = max, v ss < v in < v cc -1 +1 a i oz off state output leakage current v cc = max, v ss < v in < v cc , ce or oe > v ih or we < v il -1 +1 a v ih input high voltage 2.2 v cc + 0.5 v v il input low voltage v ss ? 0.5 0.8 v v oh output high voltage i out = ?4 ma 2.4 v v ol output low voltage i out = 8 ma 0.4 v data retention and endurance parameter description min unit data r data retention 100 years nv c nonvolatile store operations 1,000 k note 3. ce > v ih will not produce standby current levels until any nonvolatile cycle in progress has timed out. [+] feedback
STK16C88-3 document number: 001-50594 rev. ** page 7 of 14 capacitance in the following table, the capacitance parameters are listed. [4] parameter description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 0 to 3.0 v 5pf c out output capacitance 7 pf thermal resistance in the following table, the thermal resistance parameters are listed. [4] parameter description test conditions 28-pdip unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and proce- dures for measuring thermal impedance, per eia / jesd51. tbd c/w jc thermal resistance (junction to case) tbd c/w figure 4. ac test loads ac test conditions 3.3v output 30 pf r1 317 r2 351 input pulse levels .................................................. 0 v to 3 v input rise and fall times (10% - 90%)........................ < 5 ns input and output timing referenc e levels ......... .......... 1.5 v note 4. these parameters are guaranteed by design and are not tested. [+] feedback
STK16C88-3 document number: 001-50594 rev. ** page 8 of 14 ac switching characteristics sram read cycle parameter description 35 ns unit min max cypress parameter alt t ace t elqv chip enable access time 35 ns t rc [5] t avav, t eleh read cycle time 35 ns t aa [6] t avqv address access time 35 ns t doe t glqv output enable to data valid 15 ns t oha [6] t axqx output hold after address change 5 ns t lzce [7] t elqx chip enable to output active 5 ns t hzce [7] t ehqz chip disable to output inactive 13 ns t lzoe [7] t glqx output enable to output active 0 ns t hzoe [7] t ghqz output disable to output inactive 13 ns t pu [4] t elicch chip enable to power active 0 ns t pd [3, 4] t ehiccl chip disable to power standby 35 ns switching waveforms figure 5. sram read cycle 1: address controlled [5, 6] figure 6. sram read cycle 2: ce and oe controlled [5] w 5& w $$ w 2+$ $''5(66 '4'$7$287 '$7$9$/,' $''5(66 w 5& &( w $&( w /=&( w 3' w +=&( 2( w '2( w /=2( w +=2( '$7$9$/,' $&7,9( 67$1'%< w 38 '4'$7$287 ,&& notes 5. we must be high during sram read cycles. 6. i/o state assumes ce and oe < v il and we > v ih ; device is continuously selected. 7. measured 200 mv from steady state output voltage. [+] feedback
STK16C88-3 document number: 001-50594 rev. ** page 9 of 14 table 3. sram write cycle parameter description 35 ns unit min max cypress parameter alt t wc t avav write cycle time 35 ns t pwe t wlwh, t wleh write pulse width 25 ns t sce t elwh, t eleh chip enable to end of write 25 ns t sd t dvwh, t dveh data setup to end of write 12 ns t hd t whdx, t ehdx data hold after end of write 0 ns t aw t avwh, t aveh address setup to end of write 25 ns t sa t avwl, t avel address setup to start of write 0 ns t ha t whax, t ehax address hold after end of write 0 ns t hzwe [7,8] t wlqz write enable to output disable 13 ns t lzwe [7] t whqx output active after end of write 5 ns switching waveforms figure 7. sram write cycle 1: we controlled [9] figure 8. sram write cycle 2: ce controlled [9] t wc t sce t ha t aw t sa t pwe t sd t hd t hzwe t lzwe address ce we data in data out data valid high impedance previous data t wc address t sa t sce t ha t aw t pwe t sd t hd ce we data in data out high impedance data valid notes 8. if we is low when ce goes low, the outputs remain in the high impedance state. 9. ce or we must be greater than v ih during address transitions. [+] feedback
STK16C88-3 document number: 001-50594 rev. ** page 10 of 14 autostoreplus or power up recall parameter alt description STK16C88-3 unit min max t hrecall [10] t restore power up recall duration 550 s t store t hlhz store cycle duration 10 ms t stg [4, 6] power-down autostore slew time to ground 500 ns v reset low voltage reset level 2.4 v v switch low voltage trigger level 2.7 2.95 v switching waveforms figure 9. autostoreplus/power up recall 9 && 9 6:,7&+ 9 5(6(7 32:(583 5(&$// :( '4'$7$287 $xwr6wruh ? 9 w +5(&$// w vwj w 6725( %52:1287 $xwr6wruh3oxvh 12 5(&$// 9 && ','127*2 %(/2:9 5(6(7 %52:1287 $xwr6wruh3oxvh 5(&$// :+(1 9 && 5(78516 $%29(9 6:,7&+ 32:(583 5(&$// %52:1287 12 6725( '8(72 1265$0:5,7(6 12 5(&$// 9 && ','127*2 %(/2:9 5(6(7 notes 10. t hrecall starts from the time v cc rises above v switch . [+] feedback
STK16C88-3 document number: 001-50594 rev. ** page 11 of 14 software controlled store/recall cycle the software controlled store/recall cycle follows. [11, 12] parameter alt description 35 ns unit min max t rc t avav store/recall initiation cycle time 35 ns t sa [11] t avel address setup time 0 ns t cw [11] t eleh clock pulse width 25 ns t hace [7, 11] t elax address hold time 20 ns t recall recall duration 20 s switching waveforms figure 10. ce controlled software store/recall cycle [12] t rc t rc t sa t sce t hace t store / t recall data valid data valid 6 # s s e r d d a 1 # s s e r d d a high impedance address ce oe dq (data) notes 11. the software sequence is clocked on the falling edge of ce without involving oe (double clocking will abort the sequence). 12. the six consecutive addr esses must be read in the order listed in the mode selection table. we must be high during a ll six consecutive cycles. [+] feedback
STK16C88-3 document number: 001-50594 rev. ** page 12 of 14 ordering information speed (ns) ordering code package diagram package type operating range 35 STK16C88-3wf35 51-85017 28-pin pdip commercial STK16C88-3wf35i industrial all parts are pb-free. the above table contains final informatio n. please contact your local cypress sales representative for a vailability of these parts speed: 35 - 35 ns package: w = plastic 28-pin 600 mil dip part numbering nomenclature stk16c88 - 3w f 35 i temperature range: blank - commercial (0 to 70c) lead finish f = 100% sn (matte tin) i - industrial (-40 to 85c) [+] feedback
STK16C88-3 document number: 001-50594 rev. ** page 13 of 14 package diagrams figure 11. 28-pin (600 mil) pdip (51-85017) 51-85017 *b [+] feedback
document number: 001-50594 rev. ** revised january 29, 2009 page 14 of 14 autostore and quantumtrap are registered trademarks of cypress semiconductor corporation. all products and company names mentioned in thi s document may be the trademarks of their respective holders. STK16C88-3 ? cypress semiconductor corporation, 2008-2009. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions . cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution cente rs, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com psoc solutions general psoc.cypress.com/solutions low power/low voltage psoc.cypress.com/low-power precision analog psoc.cypress.com/precision-analog lcd drive psoc.cypress.com/lcd-drive can 2.0b psoc.cypress.com/can usb psoc.cypress.com/usb document title: STK16C88-3 256 kbit (32k x 8) autostore+ nvsram document number: 001-50594 rev. ecn no. orig. of change submission date description of change ** 2625096 gvch/pyrs 12/19/08 new data sheet [+] feedback

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